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| AT59C11/22/13 Features * * * * * * Low Voltage and Standard Voltage Operation 5.0 (VCC = 4.5V to 5.5V) 2.7 (VCC = 2.7V to 5.5V) 2.5 (VCC = 2.5V to 5.5V) 1.8 (VCC = 1.8V to 5.5V) User Selectable Internal Organization 1K: 128 x 8 or 64 x 16 2K: 256 x 8 or 128 x 16 4K: 512 x 8 or 256 x 16 4-Wire Serial Interface Self-Timed Write Cycle (10 ms max) High Reliability Endurance: 1 Million Cycles Data Retention: 100 Years 8-Pin PDIP and EIAJ SOIC Packages 4-Wire Serial CMOS E2PROMs 1K (128 x 8 or 64 x 16) 2K (256 x 8 or 128 x 16) 4K (512 x 8 or 256 x 16) Description The AT59C11/22/13 provides 1024/2048/4096 bits of serial EEPROM (Electrically Erasable Programmable Read Only Memory) organized as 64/128/256 words of 16 bits each, when the ORG Pin is connected to VCC and 128/256/512 words of 8 bits each when it is tied to ground. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT59C11/22/13 is available in space saving 8-pin PDIP and 8-pin EIAJ SOIC packages. The AT59C11/22/13 is enabled through the Chip Select pin (CS), and accessed via a 4-wire serial interface consisting of Data Input (DI), Data Output (DO), and Clock (CLK). Upon receiving a READ instruction at DI, the address is decoded and the data Pin Configurations Pin Name CS CLK DI DO GND VCC ORG RDY/BUSY Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Internal Organization Status Output (continued) 8-Pin PDIP AT59C11/22/13 8-Pin SOIC 0173J 2-89 Description (Continued) is clocked out serially on the data output pin DO, the WRITE cycle is completely self-timed and no separate ERASE cycle is required before WRITE. The WRITE cycle is only enabled when the part is in the ERASE/WRITE ENABLE state. Ready/Busy status can be monitored upon completion of a programming operation by polling the Ready/Busy pin. The AT59C11/22/13 is available in 5.0V 10%, 2.7V to 5.5V, 2.5V to 5.5V, and 1.8V to 5.5V versions. Absolute Maximum Ratings* Operating Temperature................... -55C to +125C Storage Temperature...................... -65C to +150C Voltage on Any Pin with Respect to Ground ..................... -1.0V to +7.0V Maximum Operating Voltage ........................... 6.25V DC Output Current ......................................... 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Block Diagram (1) Note: 1. When the ORG pin is connected to VCC , the x 16 organization is selected. When it is connected to ground, the x 8 organization is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x 16 organization. This feature is not available on 1.8V devices. 2-90 AT59C11/22/13 AT59C11/22/13 Pin Capacitance (1) Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted). Test Conditions COUT CIN Note: Max 5 5 Units pF pF Conditions VOUT = 0V VIN = 0V Output Capacitance (DO) Input Capacitance (CS, CLK, DI, RDY/BUSY) 1. This parameter is characterized and is not 100% tested. DC Characteristics Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.8V to +5.5V, TAC = 0C to +70C, VCC = +1.8V to +5.5V (unless otherwise noted). Symbol VCC1 VCC2 VCC3 VCC4 ICC ISB1 ISB2 ISB3 ISB4 IIL IOL VIL1 (1) VIH1 (1) VIL2 (1) VIH2 (1) VOL1 VOH1 VOL2 VOH2 Note: Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Current Standby Current Standby Current Standby Current Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Test Condition Min 1.8 2.5 2.7 4.5 READ at 1.0 MHz WRITE at 1.0 MHz CS = 0V CS = 0V CS = 0V CS = 0V Typ Max 5.5 5.5 5.5 5.5 Units V V V V mA mA A A A A A A V V V V VCC = 5.0V VCC = 1.8V VCC = 2.5V VCC = 2.7V VCC = 5.0V VIN = 0V to VCC VIN = 0V to VCC 4.5V VCC 5.5V 1.8V VCC 2.7V 4.5V VCC 5.5V 1.8V VCC 2.7V 0.5 0.5 0.0 6.0 6.0 21.0 0.1 0.1 -0.1 2.0 0.0 VCC x 0.7 2.0 2.0 0.1 10.0 10.0 30.0 1.0 1.0 0.8 VCC + 1 VCC x 0.3 VCC + 1 0.4 IOL = 2.1 mA IOH = 0.4 mA IOL = 0.15 mA IOH = -0.1 mA 2.4 0.2 VCC - 0.2 1. VIL min and VIH max are reference only and are not tested. 2-91 AC Characteristics Applicable over recommended operating range from TA = -40C to +85C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol fCLK Parameter CLK Clock Frequency Test Condition 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 0.1 Min 0 0 0 0 250 250 500 1000 250 250 500 1000 250 250 500 1000 50 50 100 200 100 100 200 400 0 100 100 200 400 250 250 500 1000 250 250 500 1000 250 250 500 1000 100 100 200 400 10 Typ Max 1 1 0.5 0.25 Units MHz tCKH CLK High Time ns tCKL CLK Low Time ns tCS Minimum CS Low Time ns tCSS CS Setup Time Relative to SK ns tDIS tCSH tDIH DI Setup Time CS Hold Time DI Hold Time Relative to SK Relative to SK Relative to SK ns ns ns tPD1 Output Delay to `1' AC Test ns tPD0 Output Delay to `0' AC Test ns tRBD CS to Status Valid AC Test ns tCZ tWC CS to DO in High Impedance Write Cycle Time AC Test CS = VIL ns ms 2-92 AT59C11/22/13 AT59C11/22/13 Instruction Set for the AT59C11 Instruction READ EWEN WRITE ERAL WRAL EWDS SB 1 1 1 1 1 1 Op Code 10XX 0011 X1XX 0010 0001 0000 Address x8 A6 - A0 XXXXXXX A6 - A0 XXXXXXX XXXXXXX XXXXXXX x 16 A5 - A0 XXXXXX A5 - A0 XXXXXX XXXXXX XXXXXX D7 - D0 D15 - D0 D7 - D0 D15 - D0 x8 Data x 16 Comments Reads data stored in memory, at specified address. Write enable must precede all programming modes. Writes memory location An - A0. Erases all memory locations. Valid only at VCC = 4.5V to 5.5V. Writes all memory locations. Valid only at VCC = 4.5V to 5.5V. Disables all programming instructions. Instruction Set for the AT59C22 Instruction READ EWEN WRITE ERAL WRAL EWDS SB 1 1 1 1 1 1 Op Code 10XX 0011 X1XX 0010 0001 0000 Address x8 A7 - A0 XXXXXXXX A7 - A0 XXXXXXXX XXXXXXXX XXXXXXXX x 16 A6 - A0 XXXXXXX A6 - A0 XXXXXXX XXXXXXX XXXXXXX D7 - D0 D15 - D0 D 7 - D0 D15 - D0 x8 Data x 16 Comments Reads data stored in memory, at specified address. Write enable must precede all programming modes. Writes memory location An - A0. Erases all memory locations. Valid only at VCC = 4.5V to 5.5V. Writes all memory locations. Valid when VCC = 5.0V 10% and Disable Register cleared. Disables all programming instructions. 2-93 Instruction Set for the AT59C13 Instruction READ EWEN WRITE ERAL WRAL EWDS SB 1 1 1 1 1 1 Op Code 10XX 0011 X1XX 0010 0001 0000 Address x8 A8 - A0 XXXXXXXXX A8 - A0 XXXXXXXXX XXXXXXXXX XXXXXXXXX x 16 A7 - A0 XXXXXXXX A7 - A0 XXXXXXXX XXXXXXXX XXXXXXXX D7 - D0 D15 - D0 D7 - D0 D15 - D0 x8 Data x 16 Comments Reads data stored in memory, at specified address. Write enable must precede all programming modes. Writes memory location An - A0. Erases all memory locations. Valid only at VCC = 4.5V to 5.5V. Writes all memory locations. Valid when VCC = 5.0V 10% and Disable Register cleared. Disables all programming instructions. 2-94 AT59C11/22/13 AT59C11/22/13 Functional Description The AT59C11/22/13 are accessed via a simple and versatile 4-wire serial communication interface. Device operation is controlled by six instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a Start Bit (logic `1') followed by the appropriate Op Code and the desired memory Address location. READ (READ): The Read (READ) instruction contains the Address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the rising edges of serial clock CLK. It should be noted that a dummy bit (logic `0') precedes the 8 or 16 bit data output string. ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the Erase/Write Enable state, programming remains enabled until an Erase/Write Disable (EWDS) instruction is executed or VCC power is removed from the part. WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location. The self-timed programming cycle starts after the last bit of data is received at serial data input pin DI. The Ready/Busy status of the AT59C11/22/13 can be determined by polling the RDY/BUSY pin. A logic `0' at RDY/BUSY indicates that programming is still in progress. A logic `1' indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic `1' state and is primarily used for testing purposes. The Ready/Busy status of the AT59C11/22/13 can be determined by polling the RDY/BUSY pin. The ERAL instruction is valid only at VCC = 5.0V 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The Ready/Busy status of the AT59C11/22/13 can be determined by polling the RDY/BUSY pin. The WRAL instruction is valid only at VCC = 5.0V 10%. ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the READ instruction is independent of both the EWEN and EWDS instructions and can be executed at any time. Timing Diagrams Synchronous Data Timing Note: 1. This is the minimum CLK period. (continued) 2-95 Organization Key for Timing Diagrams Density 1K I/O AN DN x8 A6 D7 x 16 A5 D15 x8 A7 D7 Density 2K x 16 A6 D15 x8 A8 D7 Density 4K x 16 A7 D15 Timing Diagrams (Continued) READ Timing WRITE Timing EWEN/EWDS Timing (continued) 2-96 AT59C11/22/13 AT59C11/22/13 Timing Diagrams (Continued) ERAL Timing WRAL Timing 2-97 Ordering Information tWC (max) (ms) 10 10 10 10 10 10 10 10 ICC (max) (A) 2000 800 600 80 2000 800 600 80 ISB (max) (A) 30.0 10.0 10.0 0.1 30.0 10.0 10.0 0.1 fMAX (kHz) 1000 1000 500 250 1000 1000 500 250 Ordering Code AT59C11-10PC AT59C11W-10SC AT59C11-10PC-2.7 AT59C11W-10SC-2.7 AT59C11-10PC-2.5 AT59C11W-10SC-2.5 AT59C11-10PC-1.8 AT59C11W-10SC-1.8 AT59C11-10PI AT59C11W-10SI AT59C11-10PI-2.7 AT59C11W-10SI-2.7 AT59C11-10PI-2.5 AT59C11W-10SI-2.5 AT59C11-10PI-1.8 AT59C11W-10SI-1.8 Package 8P3 8S2 8P3 8S2 8P3 8S2 8P3 8S2 8P3 8S2 8P3 8S2 8P3 8S2 8P3 8S2 Operation Range Commercial (0C to 70C) Commercial (0C to 70C) Commercial (0C to 70C) Commercial (0C to 70C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Package Type 8P3 8S2 8 Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8 Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Options Blank -2.7 -2.5 -1.8 Standard Device (4.5V to 5.5V) Low Voltage (2.7V to 5.5V) Low Voltage (2.5V to 5.5V) Low Voltage (1.8V to 5.5V) 2-98 AT59C11/22/13 AT59C11/22/13 Ordering Information tWC (max) (ms) 10 10 10 10 10 10 10 10 ICC (max) (A) 2000 800 600 80 2000 800 600 80 ISB (max) (A) 30.0 10.0 10.0 0.1 30.0 10.0 10.0 0.1 fMAX (kHz) 1000 1000 500 250 1000 1000 500 250 Ordering Code AT59C22-10PC AT59C22W-10SC AT59C22-10PC-2.7 AT59C22W-10SC-2.7 AT59C22-10PC-2.5 AT59C22W-10SC-2.5 AT59C22-10PC-1.8 AT59C22W-10SC-1.8 AT59C22-10PI AT59C22W-10SI AT59C22-10PI-2.7 AT59C22W-10SI-2.7 AT59C22-10PI-2.5 AT59C22W-10SI-2.5 AT59C22-10PI-1.8 AT59C22W-10SI-1.8 Package 8P3 8S2 8P3 8S2 8P3 8S2 8P3 8S2 8P3 8S2 8P3 8S2 8P3 8S2 8P3 8S2 Operation Range Commercial (0C to 70C) Commercial (0C to 70C) Commercial (0C to 70C) Commercial (0C to 70C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Package Type 8P3 8S2 8 Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8 Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Options Blank -2.7 -2.5 -1.8 Standard Device (4.5V to 5.5V) Low Voltage (2.7V to 5.5V) Low Voltage (2.5V to 5.5V) Low Voltage (1.8V to 5.5V) 2-99 Ordering Information tWC (max) (ms) 10 10 10 10 10 10 10 10 ICC (max) (A) 2000 800 600 80 2000 800 600 80 ISB (max) (A) 30.0 10.0 10.0 0.1 30.0 10.0 10.0 0.1 fMAX (kHz) 1000 1000 500 250 1000 1000 500 250 Ordering Code AT59C13-10PC AT59C13W-10SC AT59C13-10PC-2.7 AT59C13W-10SC-2.7 AT59C13-10PC-2.5 AT59C13W-10SC-2.5 AT59C13-10PC-1.8 AT59C13W-10SC-1.8 AT59C13-10PI AT59C13W-10SI AT59C13-10PI-2.7 AT59C13W-10SI-2.7 AT59C13-10PI-2.5 AT59C13W-10SI-2.5 AT59C13-10PI-1.8 AT59C13W-10SI-1.8 Package 8P3 8S2 8P3 8S2 8P3 8S2 8P3 8S2 8P3 8S2 8P3 8S2 8P3 8S2 8P3 8S2 Operation Range Commercial (0C to 70C) Commercial (0C to 70C) Commercial (0C to 70C) Commercial (0C to 70C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Package Type 8P3 8S2 8 Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8 Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Options Blank -2.7 -2.5 -1.8 Standard Device (4.5V to 5.5V) Low Voltage (2.7V to 5.5V) Low Voltage (2.5V to 5.5V) Low Voltage (1.8V to 5.5V) 2-100 AT59C11/22/13 |
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